IJSRET Volume 4 Issue 1, January-2018

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Chaotic Function Based Data Hiding Approach at Least Significant Bit Positions

Authors: Dilip Kumar Mishra, P.G.Scholar, Sriram Yadav, A.P. & Head

Abstract: With the increase in the digital media transfer and modification of image is very easy. So one major issue of proprietorship is raised, as copying and transferring is very soft practice. Here this paper has resolve proprietorship problem by embedding the digital data with encryption. In this work embedding of data is done by applying the Arnold’s Cat Map algorithm for randomization of pixel values. Then robustness is provided by using the AES algorithm. Finally  using spatial technique embedding of digital data is done in encrypted image. Embedding in LSB portion of the pixel this research work is robust against various attacks. Experiment is done on real data-set image. Evaluation parameter values shows that this research work has maintain the SNR, PSNR values with high robustness of the data.

A Survey on: Social Feature Based Service Rating Prediction Techniques

Authors: Madhu Rajput, P.G.Scholar, Amit Thakur, A.P.

Abstract: The Internet has made it possible to discover opinions of others on a wide range of subjects, through social media websites, such as review sites, wikis, and through online social networks. Some of website provide user rating for different product or services but they do not recommend any user to purchase. This paper focus on elaborating the user rating behavior of particular kind of services. Here techniques developed by various researchers are discussed with there requirements. In social network some inherent features are also detailed with the help of which prediction percentage may be increase.

A Survey on Different Features and Techniques for Web Service Prediction

Authors: Sonika Baisakhiya, P.G.Scholar, A.P. Jayshree Boaddh, Prof. Durgesh Wadbude.

Abstract: – Quality of Service (QoS) assurance is an important factor of service recommendation. The web services which are never been used before by users have some indefinite QoS values for that service, and hence the accurate prediction of indefinite QoS values is important for the successful consumption of Web service-dependent applications. Collaborative filtering is the technique which is broadly accepted in the prediction of indefinite QoS values as it is significant for predicting missing values. Though, collaborative filtering derived from the processing of subjective data. In this paper, we describe various collaborative filtering by QoS rating techniques applied to web service mining and addresses various collaborative filtering problems.

Internet of Things Based Smart Home Automation

Authors: Harshal S.Bhosale, Mrs. V. RPalundarkar, Priyesh S. Surve, Rahul B. Biswas

Abstract: – Home Automation is conveniences installed and designed to perform chore in your living place. Smart homes are often referred to as intelligent homes as they perform services that become part of our life. Many of the automated systems that silently perform their jobs unnoticed this is automation at its best. We live in an exciting time where more and more everyday items “things” are becoming smart! “Things” have sensors and can communicate to other “things” and can provide control to more “things”. The Internet of Things, IoT, is upon us in a huge way and people are rapidly inventing new gadgets that enhance our lives. The price of micro controllers with the ability to talk over a network keeps dropping and developers can now tinker and build things inexpensively. IoT based home automation can be achieved by using low cost ESP8266 ESPino ESP-12 WiFi Module, AVR Controller and Relay’s.

Review Article of Basic ADC Design and Issue of Old Algorithm

Authors: M. Tech. Madhusudan Singh Solanki, Associate Prof. Priyanshu Pandey

Abstract: –Analog to-digital converters (ADCs) are key design blocks and are at present embraced in numerous application fields to enhance computerized frameworks, which accomplish better exhibitions with regard the analog arrangements. With the quick progression of CMOS manufacture innovation, more signal processing capacities are actualized in the computerized space for a lower cost, bring down power utilization, higher yield, and higher re-configurability. Across the board use gives awesome significance to the design exercises, with these days to a great extent adds to the generation cost in coordinated circuit gadgets. This has as of late generated an extraordinary interest for low-control, low-voltage ADCs that can be acknowledged in a standard deep submicron CMOS innovation. Different cases of ADC applications can be found in information securing frameworks, estimation frameworks and digital correspondence frameworks likewise imaging, instrumentation frameworks. Subsequently, this work need to considered every one of the parameters and enhancing the related execution may fundamentally decrease the modern cost of an ADC producing process and enhanced the determination and configuration extraordinarily control utilization . This paper displays a 4 bit Pipeline ADC with low power dissipation executed in <0.18μm CMOS innovation with a power supply of 1.2V.

A Survey on Various Techniques and Characteristics of Text Document Fetching

Authors: M. Tech. Scholar Rajeev Kumar, Prof. Durgesh Wadbude, A.P. Jayshree Boaddh

Abstract: –Search engines are the major breakthrough on the web for retrieving the information. But List of retrieved documents contains a high percentage of duplicated and near document result. So there is the need to improve the performance of search results. In this paper text document retrieval study is done with various techniques of fetching with there implementations. Here different features for the text document retrieval is explained in detailed with there requirements as feature vary as per text analysis. Paper has brief different evaluation parameters for the study and comparison of relevant documents techniques.

An Rob-frugal Based Data Distribution Approach By Utilizing Frequent Pattern Tree Rules

Authors: M. Tech. Scholar Ankit Saini, A.P. Jayshree Boaddh, Prof. Durgesh Wadbude

Abstract: –– Information sharing among the organizations is a general movement in a few zones like business advancement and showcasing. As portion of the sensitive rules that should be kept private might be revealed and such revelation of sensitive patterns may impacts the benefits of the organization that possess the information. Consequently the principles which are sensitive must be covered before sharing the information. In this paper to provide secure data sharing sensitive rules are perturbed first which was found by frequent pattern tree. Here sensitive set of rules are perturbed by substitution with rob-frugal mixing. This type of substitution reduces the risk and increase the utility of the dataset as compared to other methods. Analysis is done on genuine dataset. Results demonstrates that proposed work is better as contrast with different past methodologies on the premise of assessment parameters.

A Implementation of High Speed On-Chip Monitoring Circuit By Using SAR Based ADC Design

Authors: M. Tech. Madhusudan Singh Solanki, Associate Prof. Priyanshu Pandey

Abstract: –– An 16-bit pipelined analog-to digital converter (ADC) is designed in this thesis. The pipelined architecture realizes the high-speed and high-resolution. To reduce some complexities of flash ADC pipeline ADC is used. The calibration schemes of pipelined ADC limit absolute and relative accuracy. Deviations in residue amplifier gain results due to low intrinsic gain of transistors, and mismatching between all the capacitors of capacitance 1pF result in both deviations in residue amplifier gain and DAC nonlinearity in a pipelined ADC. To image the world, a low-power CMOS image sensor array is required in the vision processor. The image sensor array is typically formed through photo diodes and analog to digital converter (ADC). To achieve low power acquisition, a low-power mid-resolution ADC is necessary. Digital correction allows also to use very low power dynamic comparators. The multiplying D/A converters (MDACs) utilize a modified folded dynamic amplifier .In this enables to the use of dynamic amplifiers in a pipeline ADC. In addition, the dynamic amplifier offers both clock scalability and high-speed operation even with a scaled supply voltage. Using the above techniques, a 16 bit prototype ADC achieves a conversion rate of 160 MS/s with a supply voltage of 0.55 V. Therefore, the combination of interpolated pipeline architecture and dynamic residue amplifiers demonstrates the feasibility of ultra-low voltage high-speed analog circuit design. To implement the whole system a low-power and small size capacitance value sensing readout circuit is required. Also, it has to be integrated together with the back-end low-power current-mode ADC on the same chip. The low-power current-mode ADC has been designed and fabricated with TSMC 0.18um CMOS technology. In the simulation result, the power consumption for 6-bit ADC was 6 W, with a power supply of 0.65 V.

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