Authors: Sushma P S Assistant Professor, Chiranthan M Y, Jayanth K M, D P Rajashekar, Suresh B
Abstract: Power consumption and computational speed are important factors in modern digital systems. This project presents a 32-Bit Vedic ALU with Low Power Mode using System Verilog. The design employs the Urdhva Tiryakbhyam algorithm for fast multiplication and incorporates operand isolation and clock gating techniques to reduce power consumption. The ALU performs arithmetic, logical, and shift operations efficiently while maintaining high performance. The proposed system provides a high-speed, reliable, and power-efficient solution for embedded systems and processor applications.
