Authors: Patwari Kavyanjali Pramod, Kamble Akanksha Laxman, Sarjine Saniya Janardan, Prof. S. S. Lohote, Prof. M. S. Nalawade, Dr. V. M. Dhede
Abstract: Integrated circuits are now designed, fabricated, tested and packaged by many different organisations spread across the world. This distributed supply chain lowers cost but also creates opportunities for an untrusted party to insert malicious logic, copy intellectual property, overbuild chips, recycle used parts as new, or extract secret keys from a working device. Hardware security in VLSI studies these threats and the design techniques that defend against them. This review classifies the threats by the life-cycle stage at which they arise and by the asset they target, and then surveys the main families of countermeasures: hardware Trojan detection, logic locking and obfuscation, split manufacturing, physical unclonable functions, side-channel and fault-injection resistance, and secure boot built on a hardware root of trust. For each family the operating principle, representative studies and known weaknesses are discussed. A life-cycle security architecture is then presented that maps each protection to the stage of design, fabrication, test and field deployment where it applies. The comparison shows that no single technique secures a chip, and that defence in depth across the life cycle is required. Open problems such as attacks on logic locking, the reliability of PUF responses and the cost of security verification are identified as directions for further work.
DOI: https://doi.org/10.5281/zenodo.23857172
