Authors: Harishankar T, Dr.T.R.Ganesh Babu
Abstract: In the context of their growing use in critical fields of application, like aviation electronics, automotive control systems, and industrial automation, FPGA circuits' operation must be guaranteed against both soft errors and any other defects that may arise during run-time. This paper analyzes in depth an approach for implementing Totally Self-Checking (TSC) comparators for online diagnostics in FPGAs in a way which maximizes its effectiveness in terms of test pattern complexity and hardware overhead. In particular, the presented technique utilizes the circuitry features of Look-Up Tables (LUTs) to provide comprehensive online testing with a number of test vectors proportional to O(n), while guaranteeing complete fault coverage and regardless of the specific LUTs configuration. The results of a comparison among recent techniques for implementing TSC, both BIST-based and Dual Modular Redundancy (DMR), show that the described solution offers an outstandingly effective performance with regard to SER (0.055 FIT).
DOI: https://doi.org/10.5281/zenodo.20233433
