Authors: Mr.K.Ch.Malla Reddy, Mr.M.Ramana Reddy, Muthakapalli Sai Sravani, Tadi Kranmai, Chinamanagonda Ranga Gayathri, Kothakota Vara Lakshmi
Abstract: A multiplier is an essential part of many extremely large scale integration systems and finds extensive application in digital circuits for innumerable arithmetic calculations. One of the most fundamental operations in digital technology is multiplication, and hardware multipliers are essential for quick computing and efficient data processing. There have been several design approaches to multipliers that focus on surface area and energy efficiency in response to the desire for high-performance, low-power multipliers. Our study presents a 4-bit field multiplier with improved energy efficiency compared to conventional designs, using a modified gate-diffusion input (MGDI) cell architecture. The energy consumption of the MGDI-based multiplier is significantly reduced to 1.109861 mW without sacrificing any of the essential operating efficiencies. Thorough simulations have been conducted to showcase the performance of the 4-bit MGDI multiplier, which was meticulously constructed utilizing Tanner EDA tools. Low power, 4-bit multiplier, time delay, transistor count, modified gate diffusion input (MGDI) are some of the keywords.
DOI: http://doi.org/10.5281/zenodo.20394671
