Authors: Faaiq Mushtaq
Abstract: Silent data corruptions or SDCs are computational errors that produce a wrong but plausible result with no crash, no exception and no flag of any kind. For decades the working assumption in systems design was that a tested processor either computes correctly or fails loudly. Recent measurement studies from Meta, Google and Alibaba have overturned that assumption: mercurial cores that occasionally miscompute at rates far above what fault injection studies predicted are now a documented, recurring phenomenon in hyperscale fleets. This paper argues that the drivers behind SDCs, transistor density, lower operating voltages and sheer deployment scale, are structural rather than transient and that the problem will intensify over the next decade as workloads move toward quantized, low precision AI training and toward radiation exposed space computing. Because full hardware correction is prohibitively expensive and the space of possible fault sites is too large to fully screen, this paper surveys algorithmic fault tolerance, particularly checksum based approaches descended from classical ABFT, as a lightweight, mathematically grounded complement to hardware mitigation. It closes by proposing a concrete thesis direction: characterizing when a modest, bounded performance cost is worth paying to catch a corrupted core before its errors propagate through a distributed system or a multi week training run.
