Authors: Assistant Professor Mainka Saharan
Abstract: This Paper describes the high speed multiplier by using Booth Algorithm. Booth algorithm produces less delay in comparison with a normal multiplication process and it also moderates the number of partial products. We also proposed a new hybrid CLA from the existing hierarchical CLA which exhibits high performance in terms of computation, power consumption and area. Area, delay and power complexities of the resulting design are reported. Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement representation in efficient way, i.e., less number of additions/subtractions required.
